Prasanth Chatarasi


Ph.D.   2017-2020, Computer Science, Georgia Institute of Technology
M.S.     2014-2017, Computer Science, Rice University
B.Tech. 2008-2012, Computer Science and Engineering, IIT Hyderabad

email: cprasanth at gatech dot edu

 

About

I recently finished my Ph.D. under the supervision of Vivek Sarkar and Jun Shirako in the Habanero Extreme Scale Software Research Laboratory at Georgia Tech in Atlanta, GA. My research focuses on advancing compiler optimizations for high-performance applications on general-purpose and domain-specific parallel architectures. In the last two years, I have focused on advancing compilers for mapping Deep Learning (DNN) operators onto flexible spatial accelerators, specialized SIMD units (e.g., Xilinx Versal AI Engine), and thread-migratory architecture (e.g., EMU). In the past, I focused on enhancing traditional compilation techniques for both sequential and explicitly parallel programs for performance optimizations and debugging on modern general-purpose architectures (e.g., Multi-core CPUs, SIMD units, and GPUs).

Experience

  • Summer 2019: Machine Learning & Compiler Research Intern in Kees Visser's group at Xilinx Research labs for Xilinx Versal architecture

  • Summer 2018: Multi-Core Heterogeneous Compiler Intern in Vinod Kathail's group on compilers for Xilinx Versal architecture .

  • Summer 2016: Research visitor in the PARKAS research group at INRIA & ENS Paris, and mentored by Albert Cohen .

  • May 2012 - Aug 2014: Software engineer at Microsoft, Hyderabad.

  • Summer 2011: Research intern in MCL research group at IISc Bangalore, and mentored by Uday Bondhugula .

 

Theses

  1. [Ph.D. Thesis] "Advancing Compiler Optimizations for General-Purpose and Domain-Specific Parallel Architectures" [Slides]
    Advisor: Prof. Vivek Sarkar, and Dr. Jun Shirako
    School of Computer Science, Georgia Institute of Technology (Defended July 2020).
  2. [M.S. Thesis] "Extending the Polyhedral Compilation Model for Debugging and Optimization of SPMD-style Explicitly-Parallel Programs" [Slides]
    Advisor: Prof. Vivek Sarkar, and Dr. Jun Shirako
    Computer Science, Rice University (Defended April 2017).
  3. [B.Tech Thesis] "Techniques for Combining Testing and Verification for Efficient Assertion Checking in Sequential Programs"
    Advisor: Dr. Aditya Nori, and Prof. M.V. PandurangaRao
    Computer Science, IIT Hyderabad (Defended April 2012).
 

Research Projects

  1. Optimizing Deep Learning (DNN) Operators on Spatial Architectures

    This line of work focuses on developing cost models and compiler technologies for optimizing rapidly emerging DNN operators (building blocks of deep learning models, e.g., CONV2D, GEMM) on to flexible spatial architectures and specialized SIMD units (e.g., Xilinx Versal AI Engine).

    1. "Marvel: A Data-centric Compiler for DNN Operators on Spatial Accelerators"
      Prasanth Chatarasi, Hyoukjun Kwon, Natesh Raina, Saurabh Malik, Vaisakh Haridas, Angshuman Parashar, Michael Pellauer, Tushar Krishna, and Vivek Sarkar,
      (Under submission)
    2. [MICRO'20 Tutorial] "MAESTRO: A Data-Centric Approach for Hardware and Mapping Explorations for Deep Learning Accelerators" [Videos]
      Tushar Krishna, Michael Pellauer, Prasanth Chatarasi, Geonhwa Jeong, and Sheng-Chun (Felix) Kao
      53rd IEEE/ACM International Symposium on Microarchitecture (MICRO'20)
    3. [HPEC'20] "Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine" [Slides] [Video]
      Prasanth Chatarasi, Stephen Neuendorffer, Samuel Bayliss, Kees Vissers, and Vivek Sarkar
      Proceedings of the 24th IEEE High Performance Extreme Computing Conference (HPEC'20)
    4. [IEEE MICRO Top Picks 2020] "MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings"
      Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, and Tushar Krishna,
      Proceedings of the IEEE MICRO Top Picks 2020
    5. [MICRO'19] "Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach"
      Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, and Tushar Krishna,
      Proceedings of the 52nd IEEE/ACM International Symposium on Microarchitecture (MICRO'19)
      (Selected for IEEE MICRO Top Picks 2020)
    6. [HPCA'19 Tutorial] "Enabling Rapid Design Space Exploration and Prototyping of DNN Accelerators"
      Tushar Krishna, Michael Pellauer, Hyoukjun Kwon, Prasanth Chatarasi, and Zhongyuan Zhao
  2. Optimizing Graph Analytics and Sparse linear algebra on a Near memory and Thread migratory hardware (EMU)

    This project focuses on advancing compiler optimizations for graph analytics and sparse linear algebra on a thread migratory architecture (EMU) introduced for weak-locality applications.

    1. [ICRC'19] "Experimental Insights from the Rogues Gallery Testbed"
      Jeffrey Young, Jason Riedy, Thomas M. Conte, Vivek Sarkar, Prasanth Chatarasi, and Srisehan Srikanth,
      Proceedings of the 4th IEEE International Conference on Rebooting Computing (ICRC 2019)
    2. [MCHPC'18] "A Preliminary Study of Compiler Transformations for Graph Applications on the Emu System" [Slides]
      Prasanth Chatarasi, and Vivek Sarkar,
      Proceedings of the 2nd International Workshop on Memory Centric High Performance Computing (MCHPC) held in conjunction with SC18

  3. Unification of Storage Transformations with Loop Transformations

    This project focuses on systematic integration of multiple storage transformations (e.g., renaming techniques) with loop transformations in a single framework to coordinate their benefits for optimizing programs for higher performance.

    1. [LCPC'18] "A Unified Approach to Variable Renaming for Enhanced Vectorization" [Slides]
      Prasanth Chatarasi, Jun Shirako, Albert Cohen, and Vivek Sarkar,
      Proceedings of the 31st International Workshop on Languages and Compilers for Parallel Computing (LCPC'18)

  4. Compiler Analysis for Debugging and Optimizations of Explicitly-Parallel programs

    This project is motivated by the observation that software with explicit parallelism is on the rise. Our work focuses on extending compiler analysis techniques to debug and optimize explicitly- parallel programs (loop-level, task-level, and SPMD-style).

    1. [LCPC'16] "An Extended Polyhedral Model for SPMD Programs and Its Use in Static Data Race Detection" [Slides]
      Prasanth Chatarasi, Jun Shirako, Martin Kong, and Vivek Sarkar,
      Proceedings of the 29th International Workshop on Languages and Compilers for Parallel Computing (LCPC'16)
    2. [PACT'15 (SRC) Poster] "Extending Polyhedral Model for Analysis and Transformation of OpenMP Programs"
      Prasanth Chatarasi, and Vivek Sarkar,
      Proceedings of the 24th International Conference on Parallel Architecture and Compilation (PACT'15)
    3. [PACT'15] "Polyhedral Optimizations of Explicitly Parallel Program" [Slides]
      Prasanth Chatarasi, Jun Shirako, and Vivek Sarkar,
      Proceedings of the 24th International Conference on Parallel Architecture and Compilation (PACT'15)
      (One of four papers selected for Best Paper session)
    4. [Interview] "Prasanth Chatarasi on Compilers and Mentors"
      Interviewed by Carlyn Chatfield, Rice University.

 

Research-level Courses (Selected)

  1. ECE 8893: Hardware Acceleration for Machine Learning
  2. ECE 8823: Interconnection Networks for High-Performance Systems
  3. CS 7290: Advanced Micro Architecture
  4. COMP 526: High Performance Computer Architecture
  5. COMP 522: Multi-core Computing
  6. COMP 515: Advanced Compilation for Vector and Parallel Processors
  7. COMP 512: Advanced Compiler Construction
  8. COMP 557: Artificial Intelligence
 

Service

  1. Mentor for two undergraduate students at IIT Hyderabad as part of the IITH Alumni-Student Mentorship program
  2. Reviewer for TACO 2020
  3. Sub reviewer for LCPC 2020, DAC 2020, LCPC 2019, LCPC 2018 and IEEE Cluster 2018
  4. Member of Artifact Evaluation Committee for CGO-PPoPP 2016, CGO-PPoPP 2017
 

Awards and Achievements

  1. IEEE MICRO Top Picks, 2020
  2. Patent Achievement Award from Xilinx, 2019
  3. Selected for final round in Qualcomm Innovation Fellowship, 2019
  4. Nominated for PACT'15 best paper session, 2015
  5. Institute Silver Medal, IIT Hyderabad -- Awarded for being the Top 1 among the students of Computer Science (2008-12) batch
  6. Institute Academic Excellence Award, IIT Hyderabad -- Awarded by Dr. Abdul Kalam, Former President of India, 2011
  7. Todai-IIT Undergraduate Student Scholarship for all the four years (2008-2012)